1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a technique of performing easy and highly accurate phase management between a plurality of clock domains in synchronization with each other by means of a PLL (phase locked loop) circuit.
2. Description of the Background Art
FIG. 19 is a circuit diagram showing phase management between a plurality of clock domains in a conventional semiconductor integrated circuit which operates in synchronization with clock signals.
A PLL circuit 501 includes a reference clock input terminal 506 to which a reference clock is inputted and a feedback clock input terminal 507 to which a feedback clock is inputted. The PLL circuit 501 further includes an A clock output terminal 508 outputting an A clock, which is connected to an input terminal of a CMOS buffer circuit 510. An A clock from the A clock output terminal 508 will be referred to as OUT-A. The CMOS buffer circuit 510 has a delay value Td for use in phase management between the clock domains. An output part of the CMOS buffer circuit 510 is connected to an input terminal of an A clock driver 502 serving as a clock distributing circuit. An A clock distributed by the A clock driver 502 is transmitted to an A clock domain 504. An A clock on the A clock domain 504 is inputted to the feedback clock input terminal 507 of the PLL circuit 501. The PLL circuit 501 further includes a B clock output terminal 509 outputting a B clock. A B clock from the B clock output terminal 509 will be referred to as OUT-B. The B clock output terminal 509 is connected to an input terminal of a B clock driver 503 serving as a clock distributing circuit. A B clock distributed by the B clock driver 503 is transmitted to a B clock domain 505.
Next, the operation of the circuit shown in FIG. 19 will be described.
The PLL circuit 501 generates A clock and B clock each having a predetermined frequency and phase based on a reference clock inputted to the reference clock input terminal 506 and a feedback clock inputted to the feedback clock input terminal 507. The A clock and B clock differ in frequency but are in phase with each other.
An A clock outputted from the A clock output terminal 508 is delayed by Td at the CMOS buffer circuit 510, and is thereafter inputted to the A clock driver 502. The A clock driver 502 distributes the A clock to the A clock domain 504. A B clock outputted from the B clock output terminal 509 is inputted to the B clock driver 503. The B clock driver 503 distributes the B clock to the B clock domain 505. An example in which a plurality of clocks are distributed within a semiconductor integrated circuit device is described in U.S. Pat. No. 5,270,592 entitled “CLOCK SUPPLY CIRCUIT LAYOUT IN A CIRCUIT AREA”, and an example in which a PLL circuit is formed in a semiconductor integrated circuit device for generating clock signals is described in U.S. Pat. No. 4,689,581 entitled “INTEGRATED CIRCUIT PHASE LOCKED LOOP TIMING APPARATUS” and “A Dual PLL Based Multi Frequency Clock Distribution Scheme” (1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 84-85).
Generally, the A clock transmitted to the A clock domain 504 and the B clock transmitted to the B clock domain 505 need to be managed to keep a predetermined phase difference therebetween. On the other hand, when the A clock driver 502 and B clock driver 503 have different delay values from each other, the phase difference between the A clock inputted to the A clock domain 504 and the B clock inputted to the B clock domain 505 is somewhat different from the predetermined phase difference. Thus, management of the phase difference between the A and B clocks has been performed by estimating the respective delay values of the A clock driver 502 and B clock driver 503 by circuit simulations and providing the desired delay value Td for the CMOS buffer circuit 510 factoring in the estimated difference in the delay values.
Phase management between a plurality of clock domains in a conventional semiconductor integrated circuit has been performed as described above. Thus, a problem arises in that estimating delay values by circuit simulations is time-consuming, causing the design period to be prolonged.
Another problem arises in that an estimation error is so great that the phase management is degraded in accuracy.